Advanced Computer Architecture-II (V-U)

A Simple Network, Network Topology, Internetworking (V-U)

Basics of Computer Hardware Design, Single Cycle Design: Data Path Design, Control Design (V-U)

Cache Performance Metrics, Cache Designs, Addressing Techniques (V-U)

Cache Performance, Reducing Miss Penalty (V-U)

Case Studies (V-U)

Classification of Cache Misses, Reducing Cache Miss Rate (V-U)

Concept of Cache Memory, Principle of Locality, Cache Addressing Techniques (V-U)

ISA Taxonomy, Memory Addressing Modes, Types of Operands, Types of Operations (V-U)

Correlating Branch Predictors, Tournament Predictor (V-U)

Key Components of Pipeline Datapath (V-U)

Disk Storage Systems, Interfacing Storage Devices (V-U)

Limitations of ILP (V-U)

DSP Media Operations, ISA Performance Putting it all Together (V-U)

Longer Pipelines – FP Instructions, Loop Level Parallelism, FP Loop Hazards (V-U)

Dynamic Branch Prediction, Branch Prediction Buffer (V-U)

Main Memory Performance, Virtual Memory Performance (V-U)

Eliminating Dependent Computations, Software Pipelining, Trace Scheduling, Superblocks (V-U)

Multiprocessor Cache Coherence, Enforcing Coherence, Performance of Cache Coherence Schemes (V-U)

Example of Invalidation Scheme, Coherence in Distributed Memory Architecture (V-U)

Parallel Processing, Parallel Processing Architectures (V-U)

Example of Single Cycle Design, Multi Cycle Design: Datapath (V-U)

Performance of Multiprocessors with: Symmetric Shared-Memory and Distributed Shared Memory (V-U)

Features of Multi Cycle Design, Introduction to Pipeline Datapath (V-U)

Placement and Replacement Policies, Cache Write Strategy, Cache Performance Enhancement (V-U)

Growth in Processor Performance (V-U)