Advanced Computer Architecture-II (V-U)

Reducing Miss Penalty or Miss Rate using Parallelism, Reducing Hit Time (V-U)

H/W Support at Compile Time (Cont.), Speculation Mechanism: H/W Vs. S/W (V-U)

Redundant Array of Inexpensive Disks, I/O Benchmarks (V-U)

H/W Support at Compile Time (V-U)

Review Lecture (V-U)

Hardware-based Speculations, Speculating on the Outcome of Branches (V-U)

Software Approaches to Exploit ILP (V-U)

History and Introduction (V-U)

Static Multiple Issue: VLIW Approach, Detecting and Enhancing Loop Level Parallelism (V-U)

I/O Interconnect Trends, Bus-based Interconnect, Bus Standards (V-U)

I/O Performance, Concluding: Quantitative Principles (V-U)

Storage Technologies, RAM and Enhanced DRAM, Disk Storage (V-U)

Structural Hazards, Data Hazards, Control Hazards (V-U)

In-order Execution, Out-of-Order Execution, Scoreboard Technique (V-U)

Superscalar Processors (V-U)

Instruction Set Encoding, MIPS Instruction Set (V-U)

Switch Topologies, Clusters (V-U)

Internetworks, Clusters (V-U)

Tomasulo's Approach (V-U)

Virtual Memory Address Translation, Protection of Multiple Processes Sharing Memory (V-U)