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CPU Design (V-U)
Course:
Advance Computer Architecture (V-U)
Discipline:
Applied Sciences
Institute:
Virtual University
Instructor(s):
Dr. M. Ashraf Chughtai
Level:
Graduate
Advance Computer Architecture (V-U)
CISC and RISC Architectures (V-U)
Communication Medium and Network Topologies (V-U)
Components of Memory Systems (V-U)
Control Unit Design (V-U)
CPU Design (V-U)
Data forwarding and Instruction Level Parallelism (V-U)
Description of FALCON-A and EAGLE using RTL (V-U)
Design Process for ISA of FALCON-A (V-U)
Designing Parallel Input and Output Ports (V-U)
Direct Memory Access (DMA) (V-U)
Error Control and RAID (V-U)
External FALCON-A CPU (V-U)
FALCON-E and ISA Comparison (V-U)
FALSIM (V-U)
Floating-Point Arithmetic (V-U)
Hazards in Pipelining (V-U)
I/O Subsystems (V-U)
Input Output Interface (V-U)
Instruction Set Architecture (V-U)
Interrupt Driven I/O (V-U)
Interrupt Hardware and Software (V-U)
Interrupt Priority and Nested Interrupts (V-U)
Introduction (V-U)
ISA and Instruction Formats (V-U)
ISA of FALCON-A (contd..) (V-U)
Logic Design and Control Signals Generation in SRC (V-U)
Machine Reset and Machine Exceptions (V-U)
Magnetic Disk Drives (V-U)
Measurment of performance and Introduction to SRC Processor (V-U)
Memory Modules (V-U)
Micro Programming (V-U)
Multiplication and Division of Integers (V-U)
Networks (V-U)
Number Systems and Radix Conversion (V-U)
Numerical Examples of DRAM and Cache (V-U)
Performance of I/O Subsystems (V-U)
Pipelined SRC (V-U)
Pipelining (V-U)
Programmed I/O (V-U)
Reverse assembly and Description of SRC in RTL (V-U)
Review (V-U)
RTL Using Digital Logic Circuits (V-U)
Structural RTL Description of the FALCON-A (V-U)
The Cache (V-U)
Virtual Memory (V-U)
