Virtual University

Dynamic Branch Prediction, Branch Prediction Buffer (V-U)

Main Memory Performance, Virtual Memory Performance (V-U)

Eliminating Dependent Computations, Software Pipelining, Trace Scheduling, Superblocks (V-U)

Multiprocessor Cache Coherence, Enforcing Coherence, Performance of Cache Coherence Schemes (V-U)

Example of Invalidation Scheme, Coherence in Distributed Memory Architecture (V-U)

Parallel Processing, Parallel Processing Architectures (V-U)

Example of Single Cycle Design, Multi Cycle Design: Datapath (V-U)

Performance of Multiprocessors with: Symmetric Shared-Memory and Distributed Shared Memory (V-U)

Features of Multi Cycle Design, Introduction to Pipeline Datapath (V-U)

Placement and Replacement Policies, Cache Write Strategy, Cache Performance Enhancement (V-U)

Growth in Processor Performance (V-U)

Reducing Miss Penalty or Miss Rate using Parallelism, Reducing Hit Time (V-U)

H/W Support at Compile Time (Cont.), Speculation Mechanism: H/W Vs. S/W (V-U)

Redundant Array of Inexpensive Disks, I/O Benchmarks (V-U)

H/W Support at Compile Time (V-U)

Review Lecture (V-U)

Hardware-based Speculations, Speculating on the Outcome of Branches (V-U)

Software Approaches to Exploit ILP (V-U)

History and Introduction (V-U)

Static Multiple Issue: VLIW Approach, Detecting and Enhancing Loop Level Parallelism (V-U)

I/O Interconnect Trends, Bus-based Interconnect, Bus Standards (V-U)

Storage Technologies, RAM and Enhanced DRAM, Disk Storage (V-U)

I/O Performance, Concluding: Quantitative Principles (V-U)

Structural Hazards, Data Hazards, Control Hazards (V-U)

In-order Execution, Out-of-Order Execution, Scoreboard Technique (V-U)