Digital Logic Design (V-U)

Design Example Traffic Signal Control System (V-U)

Shift Registers (V-U)

Design of Synchronous Counters (V-U)

Special Type of Memories (V-U)

Digital Circuits and Operational Characteristics (V-U)

State Assignment (V-U)

Digital Clock (V-U)

Successive –Approximation Analogue to Digital Converter (V-U)

Down Counters (V-U)

The 555 Timer (V-U)

FLASH Memory Array (V-U)

Implementation of an Odd-Parity Generator Circuit (V-U)

The 74XX138 3-to-8 Decoder (V-U)

The GAL16V8 (V-U)

Implementing constant 0s and 1s (V-U)

Timing diagram of a Synchronous Decoder Counter (V-U)

Introduction & Overview to Digital Logic (V-U)

Up/Down Counter (V-U)

Introduction to FPGAs (V-U)

Karnaugh Map & Boolean Expression Simplification (contd.) (V-U)